I am very new to VERILOG programming as my first program i have wrote an andgate program in the gate level abstraction with inputs x, y and output z. Here is my first program
module andgate (z, x, y);
input x, y;
output z;
wire x, y;
reg z; ---------- // I end up with an Syntax Error if i use this statement.
and (z,x,y);
endmodule
Please help me in understanding the reason why we are unable to declare reg z; at this instance
verilog basically calls anything that is assigned in an always or initial block a "reg", even if it doesn't infer a register. things assigned outside are generally declared as wire. systemverilog defines a "logic" type that can be used in most cases.