Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

verilog project..plzz help.....

Status
Not open for further replies.
R

raghava_kumar85

Newbie level 6
Newbie level 6
Joined
Jan 1, 2006
Messages
14
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,392
verilog project

verilog HDL code for the area coefficient architecture using DTLMS algorithm
and
verilog HDL code of the area coefficient architecture using sign-data DTLMS..
 

hi, if you have any book, specification or design document based on this, post it. Let us go over it and try to come up with the code. If i'm not mistaken, it is Delayed trigonometric least-mean-square algorithm, right ?
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top