Verilog Program to count pulse within specified time using DEO Nano FPGA

I am designing a FPGA using DEO-Nano Development Kit. I need a source code in verilog HDL which can count the number of pulses. The pulses are to be input into FPGA from external hardware after the enable signal is triggered to the external hardware. And the counted pulses are to be read or displayed in PC. I have no idea how to begin. Please could you help me ?

Step 1 - look at the programming language & syntax
Step 2 - Write the pseudo code you want & then someone here will help you fill in the missing pieces.
for example

You can first partition your project into 3 parts.
1> Data entering the FPGA(your design unit) from an external source: Do you have any info on how the data will be fed in? What communication protocol the incoming data would follow? If not you must collect info on this.
2> Your design unit in Verilog: From your description the design shouldn't be complicated. Write the logic and develop a suitable test-bench to do functional verification.
3> Data leaving the FPGA(your design unit): Again you have to be clear of how the data needs to be transferred out, protocol to be used, etc.

Once you have the answers to <1> and <3>, start developing your Verilog HDL code accordingly. Don't worry about the physical FPGA connections right away. Model your test-bench bench in such a way that it will be able to feed in the pulses and the enable signal to your HDL design. Your test-bench should also be able to capture the count_value send out from your design. During simulation you can use $display(...) to print out the count_value in the simulation tool transcript window.
In this way you can make sure that you design works in simulation and if you can achieve this, it would be significant progress.

Note: I see that you are new in this forum. Here we don't give out codes. Rather members post their codes or their exact difficulty area and others try to solve them.