Non AMP

[SOLVED] Verilog print out %d longer than 32bit

Thread starter childs72
Start date Mar 27, 2019

Status: Not open for further replies.

Mar 27, 2019

#1

C

childs72

Member level 1

Good day,

Anyone can share how to (in Verilog) print out signal >32bit using %d?

Example I used:

Code Verilog - [expand]
1
2
reg [49:0] my_var;
initial $display("%d", my_var);

The result I got is not my_var, thus i suspect %d is limited to 32bit. Is there any way I can print out my_var in decimal format?

Thanks!

Status: Not open for further replies.

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