Verilog Modules not being instantiated in Quartus II

[zerovirus123]

I created a project with a few modules included. When I compiled my design, there are no errors of any sort. However, when I viewed my project with the Netlist Viewer (post-fitting), I could not see any of my module files being instantiated. All I see are the inputs and outputs of the whole project. Does it mean that my modules are not being instantiated properly? Thanks.

 

[FvM]

You'll find the answer by reviewing the compilation report thoroughly. Most likely the logic has been removed during synthesis because no top level output depends on it.

Presumed the module contains meaningful logic, the reason might be a missing clock connection, module is stuck in reset, or something similar.