rvidya
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hi,
In Verilog, suppose I have a module A inside which a smaller module B should be instantiated. Suppose in module B's code the first line is like :
module B(o1,o2,i1,i2);
where o1,o2 are outputs and i1,i2 are inputs of B. But suppose, while instantiation, A is not able to give both the inputs needed for i.e, A is producing only i1 and i2 is produced from a third module called module C. In such a situation how do we instantiate B in A.??
I hope the question is clear.
Thank you.
In Verilog, suppose I have a module A inside which a smaller module B should be instantiated. Suppose in module B's code the first line is like :
module B(o1,o2,i1,i2);
where o1,o2 are outputs and i1,i2 are inputs of B. But suppose, while instantiation, A is not able to give both the inputs needed for i.e, A is producing only i1 and i2 is produced from a third module called module C. In such a situation how do we instantiate B in A.??
I hope the question is clear.
Thank you.
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