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Verilog looping through computation

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javawizkid

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Hi,
I'm struggling to figure out how to implement this in verilog. I have a combinatorial chip I have created in gate level logic lets call it Z which has an input called X and an output called Y.

I can get it to compute logic by looping it through manually by going:
Code:
Z z1(w,1'b1);
Z z2(w1,w);
Z z3(w2,w1);
etc for n times.

However I want to be able to use only ONE of these chips and get it to go through a loop with a clock but I've learnt that you cannot 'call' one of these modules inside

Code:
always @ (posedge clk)
begin
...
end
So I'm not sure about how to approach this problem?

Any suggestions would be helpful.

Cheers
 
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rberek

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If I understand you correctly, I think you would have to feed the output of your module back to the input through a flip flop. The flip flop would be have a reset state of 1. If it is necessary to have the computation done N times, then you would gate the flip flop with a counter such that the flip flop output the output of your module for N clocks, then held its output constant thereafter.

r.b.
 

javawizkid

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Yes, this is what I'm trying to achieve. However, I don't know how to implement this in verilog? I can output a chip's result to a flip flop but then how do I get it to feed back to the original chip which computed the value in the first place?

Thanks
 

javawizkid

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Yes, this is what I'm trying to achieve. However, I don't know how to implement this in verilog? I can output a chip's result to a flip flop but then how do I get it to feed back to the original chip which computed the value in the first place?

Thanks
Code:
wire [79:0]out;
  reg [79:0]in;
  
  assign out = L;
  
  reg [4:0]i = 5'b00000;
  
  always @(posedge clk)
  begin
	in <= out;
	i=i+1;
  end
  
  chip s1(out,in);

endmodule
This sort of works except the chip runs when the in value is xxxx and so out becomes xx which is then set to in on the clock posed. How can I get the chip to execute only when the values are actual values and not xxxxxx?

Or how do I set the value of in to be the input L outside of the posed begin end loop?
 
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rberek

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Firstly,you are assigning a value to the wire out, but your module is already driving out. this could create an X because of multiple drivers. It would likely not synthesize.

You could assign the initial value of "in"in an initial block (if this is is not synthesizeable), or by defining a reset state for the flip flop.

As far ad I know, there is no easy way to have something ignore X's. It is up to the designer to make sure that the simulation environment does not inject X into the simulation or that RTL does not introduce it.

r.b.
 

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