#### javawizkid

##### Newbie level 3

Hi,

I'm struggling to figure out how to implement this in verilog. I have a combinatorial chip I have created in gate level logic lets call it Z which has an input called X and an output called Y.

I can get it to compute logic by looping it through manually by going:

etc for n times.

However I want to be able to use only ONE of these chips and get it to go through a loop with a clock but I've learnt that you cannot 'call' one of these modules inside

So I'm not sure about how to approach this problem?

Any suggestions would be helpful.

Cheers

I'm struggling to figure out how to implement this in verilog. I have a combinatorial chip I have created in gate level logic lets call it Z which has an input called X and an output called Y.

I can get it to compute logic by looping it through manually by going:

Code:

```
Z z1(w,1'b1);
Z z2(w1,w);
Z z3(w2,w1);
```

However I want to be able to use only ONE of these chips and get it to go through a loop with a clock but I've learnt that you cannot 'call' one of these modules inside

Code:

```
always @ (posedge clk)
begin
...
end
```

So I'm not sure about how to approach this problem?

Any suggestions would be helpful.

Cheers

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