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Verilog linting tools?

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mrflibble

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Sometimes verilog's loose typing makes me a little sad. :-( Every now and then you will make a typo, which gets silently ignored by the tools. Only your design will not work. Joy.

I know one obvious answer is: "Well now, you should VHDL! VHDL is awesome, strict typing and stuff!". No doubt, but this would also mean a new learning curve + as with all human constructs VHDL will have it's own set of flaws. So I would like to make it work with verilog.

So I am looking for verilog linting tools, preferably free ones. But I would consider a commercial one if it's features are way better than what is freely available.

I just tried verilator 3.810, and that seems to work sortof okay, except for vendor specific primitives like LUTs, PLLs, etc. For example:

Code:
verilator --bbox-unsup --lint-only test_linter.v

%Error: test_linter.v:62: Cannot find file containing module: LUT5_L
%Error: exciter/exciter_passthrough.v:62: Looked in:
%Error: exciter/exciter_passthrough.v:62:       LUT5_L
%Error: exciter/exciter_passthrough.v:62:       LUT5_L.v
%Error: exciter/exciter_passthrough.v:62:       obj_dir/LUT5_L
%Error: exciter/exciter_passthrough.v:62:       obj_dir/LUT5_L.v

So I guess the question is twofold:

1 - Does anyone have a good solution to use verilator for linting which takes care of the vendor specific primitives?
2 - Any free or commercial linting tools that can handle primitives like this (LUT, PLL, etc)?

thanks for reading. :)
 

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