Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

verilog - library cell info needed

Status
Not open for further replies.
P

powercore

Newbie level 3
Joined
Jan 15, 2003
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
UK
Activity points
12
I need to run accurately a gate-level simulation, using Verilog, and I can't find rising and falling time delay of basic gates (not to mention the complex gates I need) :( under different load conditions (i.e. 1,2,3,4 NOT gate).
Technology is not an issue. How can I extract those info from a standard cell library if I could find one?
Can anybody help?
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top