verilog integer range
It's always good, to read the specification in detail. I thought, that the guys, who are interested in the details could consult the specification by themselves. Just consider, that some aspects aren't reflected adequately in Verilog textbooks or tool handbooks.
To my opinion, the single sentence I quoted, already clarifies the difference between registers and integer in the Verilog concept. While integer with a range can be used for synthesis purposes in VHDL, there doesn't exist an equivalent in Verilog. Cause Verilog is much less typified, you basically have bit vectors, that are also treated as unsigned numbers by default, and you have signed as an option.