Verilog : how to use module as global module

[ghazalaz]

Verilog : how can i use a module as global module?

hi,
i wanna use some 2d array of registers as global in some module and change them sometime , i define them in module named memory like this:

module memory();
  reg [31:0]Inst_Mem[31:0];
  reg [31:0]Data_Mem[31:0];
  reg [31:0]RF[31:0];
  reg [5:0]PC;
end module

now i want to use these memories in another module (named run) and make changes to them,

module run( input [31:0]Ins );
  reg clk;
   ...
  initial begin
   clk = 0;
    ...
  end
  initial repeat(100)#5 clk = ~clk;
  always @(posedge clk)
  begin
    memory.PC[5:0] = memory.PC + 6'b000001 ;
    ...
  end
  
endmodule

i even can't pass them as inout parameter because they're 2d reg array

so what can i do? :-/

how can i initialize and make change to them in any module?
i will be so thankful if anybody can help (please)

 

[mrflibble]

Re: Verilog : how can i use a module as global module?

i wanna use some 2d array of registers as global in some module and change them sometime , i define them in module named memory like this:

---

Code Verilog - [expand]
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module memory();
  reg [31:0]Inst_Mem[31:0];
  reg [31:0]Data_Mem[31:0];
  reg [31:0]RF[31:0];
  reg [5:0]PC;
end module

---

Well, your "memory" module has no input or output ports. In HDL country that is the equivalent of a black box ... which you then throw in a black hole, never to be seen again. Nothing goes in, nothing comes out.

For a two in one educational moment, see for example this: https://www.asic-world.com/verilog/para_modules1.html

One, you get to see how to do inputs/outputs for your modules. Two, you get parameterization thrown in for free. Woohoo!