module Counter(
input clk,
input enable,
input reset,
output reg[31:0] Final_value,
output reg trig
);
reg[31:0] counter_out;
reg [7:0] temp;
reg [31:0] counter_result;
wire temp1;
wire temp2;
always@(posedge clk or negedge reset)
begin
if(~reset)
begin
trig<=0;
temp<=0;
counter_out<=0;
end
else if(enable==1'b1)
begin
counter_out<=counter_out+1;
temp<=temp+1;
if(temp==25)
begin
temp<=0;
trig<=~trig;
end
end
end
assign temp1=trig;
assign temp2=temp1&&clk;
always@(posedge temp2 or negedge reset)
if(~reset)
counter_result<=0;
else
begin
counter_result<=counter_result+1;
end
always@(posedge trig or negedge reset)
if(~reset)
Final_value<=0;
else
begin
Final_value<=counter_result;
end
endmodule