I have a small problem with Verilog. When I want to assign a unpacked wire array to a input array of an instance it does not work. It seems to me that I can't do it in this way?!?.
For example:
---------------
// I want to connect 1byte-width wires to a component that has also pins which are organized in a array ([7:0] pin [2:0]).
Code:
wire [7:0] input [2:0];
component instance (.pin(input)) // does not work
component instance (.pin[2:0](input[2:0]) // does not work
component instance (.pin[0](input[0]),
.pin[1](input[1]),
.pin[2](input[2])
); // does also not work
Maybe, is there anyone who can help me with this issue?
I hope there is a way to realise it.
and during instantiation you can split tmp or pass it as it is and split the bus inside the sub modeul. may be u might have got what i am trying to say. this is just one of the possibility.