[Verilog] help! a decoder with unknown number of inputs

[nickwang1982]

Here is my problem.
I have unknown number of inputs (all with 3-bit wide), depending on the system configuration. I want to design a decoder to select the input with largest value as the output. So I am using embedded ruby here, so that the configuration can be passed to RTL.
Here is my design:

[B]module[/B] decoder
(
<%  (1...NUM_INPUT).[B]each do[/B] |i| -%>
     [B]input [/B]     [2:0]  freq_<%=i%>,  
<% end -%>
     [B]output[/B]    [2:0]  decoded_freq        
)
<%  (1...NUM_INPUT-1).[B]each do[/B] |i| -%>
     [B]wire[/B]      [2:0]  x<%=i%>,
<% end -%>

  [B]integer [/B]i;
//decode logic below
  [B]assign [/B]x1 = (freq_1 > freq_2)? freq_1:freq_2;  //compare the first two inputs and select the bigger one
  [B]for [/B](i=1; i<NUM_INPUT-1;i++)                       //for-loop to do the rest
       x<%=i+1%> = (x<%=i%> > freq_<%=i+2%>)? x<%=i%>:freq_<%=i+2%>;
  [B]assign [/B]decoded_freq = x<%=NUM_INPUT-1%>;
[B]endmodule[/B]

Will this work? I am not sure about the for-loop here. Is it going to work as I want? Is there any other way to do it?

 

[FvM]

The for-loop does not work. Despite of wrong Verilog syntax (a generate scheme instead of a for loop must be used in concurrent code), a script expression can't access a Verilog loop or generate variable, it's just text processing.

The problem is that standard Verilog doesn't support structures or arrays in module ports. As state-of-the-art solution, use System Verilog. Alternatively, you have to generate the Verilog lines processing the freq_x inputs in the script language, either as nested conditional assignments or if .. else structure.

Instead of "unknown", we say parameterizable number of inputs.

 

[nickwang1982]

The for-loop does not work. Despite of wrong Verilog syntax (a generate scheme instead of a for loop must be used in concurrent code), a script expression can't access a Verilog loop or generate variable, it's just text processing.

The problem is that standard Verilog doesn't support structures or arrays in module ports. As state-of-the-art solution, use System Verilog. Alternatively, you have to generate the Verilog lines processing the freq_x inputs in the script language, either as nested conditional assignments or if .. else structure.

Instead of "unknown", we say parameterizable number of inputs.

Thank you for the answer. I see what you mean, so I have removed for-loop replacing with ruby

 //decode logic below
  assign x1 = (freq_1 > freq_2)? freq_1:freq_2;  //compare the first two inputs and select the bigger one
<% (1:NUM_INPUT-2).each do |i| -%>
       x<%=i+1%> = (x<%=i%> > freq_<%=i+2%>)? x<%=i%>:freq_<%=i+2%>;
<% end -%>
  assign decoded_freq = x<%=NUM_INPUT-1%>;

Further questions
1) Systemverilog can be used to generate parameterized module ports?

2) I am using YAML to set the parameters, using eruby to map or pass the parameters to the above code. Is it what you said about the alternative?

Thank you again.