Verilog HDL - Tutorial Recommendations

[bigdogguru]

Logic Levels Within Verilog
0 - logic zero, false condition

1 - logic one, true condition

x - unknown logic value

z - high impedance




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[bigdogguru]

Let's assume that we have a design which requires us to have counters of various width, but with the same functionality. Maybe we can assume that we have a design which requires lots of instants of different depth and width of RAMs of similar functionality. Normally what we do is creating counters of different widths and then use them. The same rule applies to the RAM we talked about.

But Verilog provides a powerful way to overcome this problem: it provides us with something called parameter; these parameters are like constants local to that particular module.


Verilog Parameterized Modules

 

[sanju_]

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Verilog Tutorial
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[sanju_]

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