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Verilog HDL - Tutorial Recommendations

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A compact collection of Verilog Designs including sequential circuits, finite state machines and advanced techniques with accompanying testbenches.

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Design rules to help in successful synthesis of Verilog designs.


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This section explains what a parameterized module is and the syntax involved initialising and re-defining parameter values.

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Delay modeling is covered by Verilog quite extensively. In terms of blocks, delays can be modeled on any level from single gates to the top of a hierarchy. That is thanks to the language which allows to define simple delays such as found in basic gates as well as lumped delays which are an overall effect of more complex combinational constructs. There are even conditional delays which are useful for circuits with multiplexed outputs. In terms of logic, delays of all states are fully modeled i.e. not only rise and fall times, but also switch-off transition. Delays can also be defined as worst, best and typical cases. This is a very powerful tool for design for manufacturability.

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An introduction and explanation of each form of delay modelling, as well as a circuit example and a module example for each.

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Verilog can model delay types within its specification for gates and buffers. Parameters that can be modelled are T_rise, T_fall and T_turnoff. To add further detail, each of the three values can have minimum, typical and maximum values.

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Specify blocks include statements to do the following:

Define pin-to-pin timing delays across module paths
Set up timing checks in the circuits
Define specparam constants

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There are two ways in which pin-to-pin delays can be expressed. A path delay can be constant for all possible conditions and independent from the rest of the circuit or it can depend on various internal or input conditions. Path Delays can therefore be either non-conditional or conditional. They must always be defined within a specify block, inside a module. A description of the syntax for defining non-conditional path delays is contained in the section on the Specify Block. In summary, the paths in a module can be defined as a number of Parallel Connections, each one specified using the => symbol, or as a set called a Full Connection, in which all paths implied using the *> symbol have an equal delay. For a module with many paths, a mix of Parallel and Full connections can be used to assign the various delays.



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This section, the final part of the delay modeling chapter, discusses some of the various system tasks that exist for the purposes of timing checks. Verilog contains many timing-check system tasks, but only the three most common tasks are discussed here: $setup, $hold and $width. Timing checks are used to verify that timing constraints are upheld, and are especially important in the simulation of high-speed sequential circuits such as microprocessors.

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The ability to model varying signal levels as produced by digital hardware is fundamentally important for the simulation of switch level circuits. This is accomplished by assigning various signal strengths as defined in Table 1. The signal strengths vary from supply level own to high impedence level, covering six distinct intermediate levels.


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Verilog Switch Level Modelling Dealing With Ambiguous Signal Strengths


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When writing software, some operations, whilst simple in concept and maths require large quantities of code to perform. This operation may be required more than once in a program. Including long procedures in the main of a program, espeicially if repeated, detracts from the flow, readability and de-bugging ease.


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Most programming languages provide a facility through which lengthy, repetitive, sections of code can be "software engineered" into more manageable routines. Verilog is no different and where common segments of code are used a "function" can be written once and called several times.


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The importance of using a structured approach when writing computer programs can be outlined by explaining some of the benefits such an approach can bring to both the writer and others wishing to understand the code.


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This section explains what a parameterized module is and the syntax involved initialising and re-defining parameter values.


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With blocking assignments each statement in the same time frame is executed in sequential order within their blocks. If there is a time delay in one line then the next statement will not be executed until this delay is over.


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A Block is a section of Verilog code within a module which can be contained within begin...end statements. In many simulations different blocks run in parallel: operations from different blocks are executed in one time slice. Within a block it is more usual for commands to be executed in a serial manner, particularly when learning the language as this approach mirrors programing languages more closely. The following two examples illustrate serial execution:




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