Verilog HDL problems pls help

[microelectronics]

else if( SW[9:7] == 3'b010 ) // STOP
begin
if( KEY[1]==0 && KEY[0]==0 )
begin
E = 6;
P = 0;
O = 1;
T = 2;
S = 3;
go = 2'b11;
KEY[0]<=1;
KEY[1]<=1;
end



pls help..what should i do to make this work?

the error that comes out says this :
Error (10137): Verilog HDL Procedural Assignment error at display1.v(63): object "KEY" on left-hand side of assignment must have a variable data type

 

[grvkpr18]

You must have declared KEY as an input. Inputs cannot be manipulated in the program. I think you should rewrite KEY as inout.

 

[aVi3467]

Your variable KEY is declared as a net and since you are assigning it values inside an always block, it needs to be declared as a Reg.

In case u cannot declare KEY as reg, for it being an input, use a temp variable, manipulate it, and do a continuous assignment to KEY from that Variable.

reg [a:b]temp_KEY;

assign KEY = temp_KEY;
...
...

else if( SW[9:7] == 3'b010 ) // STOP
begin
if( KEY[1]==0 && KEY[0]==0 )
begin
E = 6;
P = 0;
O = 1;
T = 2;
S = 3;
go = 2'b11;
temp_KEY[0]<=1;
temp_KEY[1]<=1;
end

--E

 

[microelectronics]

ooo... thank you thank you.. i shall try it out.. ^^