Verilog functionality question

[farklempt]

What does a code that looks like that do:
module unknown
#(parameter par = 200)
(
input [par-1 : 0] dout;

reg [15:0] decoder;
assign s_port = dout[200-1 -:8]
always @(*) begin
decoder = 0;
decoder[s_port] = 1'b1;
end
....

I have the following questions:
1.) What are the parameters that the always statement is monitoring? @(*)
2.) How come that decoder is defined as 0 and 1'b'1 at the same time?
3.) How come that a 16 bit decoder decodes just 8 bit. where are this 8 bit? are they 15 downto 8, 14 downto 7 ... 7 downto 0?

 

[j_andr]

   reg   [15:0] decoder;
   assign s_port = dout[200-1 -:8]
   always @(*) begin         //  monitor everything until 'end'
     decoder = 0;             //  assign decoder bits to '0'  but:
     decoder[s_port] = 1'b1;  //  decoder bit defined by 's_port' assign to '1'
   end

s_port should be 4 bits wide rather to select one of 16 bits of decoder,
or more sophisticated idea is behind it ?

 

[farklempt]

Thanks j_andr,
Very helpful.

 

[permute]

i wasn't aware that a -: existed, but I'll assume it is similar to +:. The operator uses the left side for one of the bounds, and adds/subtracts 8-1 to get the other, thus giving an 8b output.

@(*) was also added in verilog2001, and allows the simulator to determine what to wait for.

In this case, both types of assigns would work the same. The blocking assignment is actually used here, so it means something like "for the purposes of determining the output, assume all bits are 0. set one bit to 1."

"unknown" is a bad module name. "dout" is a misleading name for an input. I suggest you assume the current module is always the top module in the design, and name outputs as such. This largely prevents you from having misleading ports of "input_data" as an output, or "output_data" as an input. The same can apply to instances of modules -- name all outputs first, then connect things up.

 

[farklempt]

Thanks permute,
my understanding for the decoder and the s_port parameter is as follows:
s_port can be a ny number between 199 and 191.
Lets say that s_port = 195.
Then
decoder[195]= 'h00C3
Did I undrstand it correctly?

 

[j_andr]

my understanding for the decoder and the s_port parameter is as follows:
s_port can be a ny number between 199 and 191.
Lets say that s_port = 195.
Then
decoder[195]= 'h00C3
Did I undrstand it correctly?

I'm afraid you are wrong;
there is no declaration of s_port in the piece
of code you have sent in the initial post

reg [15:0] decoder;
assign s_port = dout[200-1 -:8]
always @(*) begin
decoder = 0;
decoder[s_port] = 1'b1;
end

I assumed the s_port is: wire [7:0];
so the 's_port' has a range from '0' to '255';

the line: decoder[s_port] = 1'b1; means:
if s_port = '0' decoder = '0000000000000001'
if s_port = '1' decoder = '0000000000000010'
...
if s_port = '6' decoder = '0000000001000000'
etc;
------

 

[farklempt]

I'm afraid you are wrong;
there is no declaration of s_port in the piece
of code you have sent in the initial post

reg [15:0] decoder;
assign s_port = dout[200-1 -:8]
always @(*) begin
decoder = 0;
decoder[s_port] = 1'b1;
end

I assumed the s_port is: wire [7:0];
so the 's_port' has a range from '0' to '255';

the line: decoder[s_port] = 1'b1; means:
if s_port = '0' decoder = '0000000000000001'
if s_port = '1' decoder = '0000000000000010'
...
if s_port = '6' decoder = '0000000001000000'
etc;
------

Thanks, it clarify the functionality of the decoder.
I missed entering the definition of s_port:

wire [2:0] s_port;
With this restriction, my understanding is that the statement
assign s_port = dout[200-1 -:8]
is equivalent to:
sport[2] = dout[193]
sport[1] = dout[192]
sport[0] = dout[191]

and as a result, the statement
decoder[s_port] = 1'b1;
is equivalent to:

if s_port = '0' decoder = '0000000000000001'
if s_port = '1' decoder = '0000000000000010'
if s_port = '2' decoder = '0000000000000100'

right?