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| module block_mul(clk, a,b,start,res,r,finish);
input [7:0] a,b;
input start,clk,res;
output [15:0] r;
output reg finish;
reg [7:0] regA, regB;
reg [16:0] regR;
reg [2:0] step;
reg swap_a, swap_b;
reg shift_r;
wire [ _______________ ] mult_out;
wire [ _______________ ] add_out;
assign mult_out= regA[3:0]*regB[3:0];
assign add_out = _______________ + regR[15:8];
assign r = regR[15:0];
always@(posedge clk) begin
if(start && step == 0) begin
regA <= a;
regB <= b;
regR <= 0;
end else begin
if(swap_a) begin
regA[7:4] ___________________ regA[3:0];
regA[3:0] ___________________ regA[7:4];
end else
regA <= regA;
if(swap_b) begin
regB <= { _______________ };
end else
regB <= regB;
if(shift_r) begin
regR[16:13] <= 0;
regR[12:4] <= _______________;
regR[3:0] <= regR[7:4];
end else if(step != 0) begin
regR[16:8] <= _______________;
regR[7:0] <= regR[7:0];
end else begin
regR <= regR;
end
end
end
always@(posedge clk) begin
if(res) begin
step <= 0;
finish <= 0;
end else begin
finish <= 0;
if(step == 0 && start) begin
step <= 1;
swap_a <= ___________________;
swap_b <= ___________________;
shift_r <= ___________________;
end else if(step == 1) begin
step <= 2;
swap_a <= ___________________;
swap_b <= ___________________;
shift_r <= ___________________;
end else if(step == 2) begin
step <= 3;
swap_a <= ___________________;
swap_b <= ___________________;
shift_r <= ___________________;
end else if(step == 3) begin
step <= 4;
swap_a <= ___________________;
swap_b <= ___________________;
shift_r <= ___________________;
end else if(step == 4) begin
step <= 0;
swap_a <= 0;
swap_b <= 0;
shift_r <= 0;
finish <= 1;
end
end
end
endmodule
module test();
reg[7:0] a,b;
wire[15:0] result;
reg clk,res,start;
wire done;
block_mul dut(clk,a,b,start,res,result,done);
always begin
clk=0; #5; clk=1; #5;
end
initial begin
$dumpvars(0,dut);
res=1; #22;
res=0;
a=63; b=63; start=1; #10
start=0; #100
a=1; b=1; start=1; #10
start=0; #100
a=255; b=255; start=1; #10
start=0; #100
a=3; b=64; start=1; #10
start=0; #100
a=4; b=128; start=1; #10
start=0; #100
a=0; b=0;
$finish;
end
endmodule |