Verilog file IO Question

[enchanter]

I am writting 8 bits counter value (16 values) to a binary file and read it back to 128 bits variable.

Input Data: 0x00, 0x01 ..... 0x0f
Output Data (Expected): 0x00010203....0f (128 bits)

My Code is here

module read_mem;

   integer fin;
   integer fout;
   reg [7:0] data8;
   reg [127:0] data128;
   integer idx;
   integer code;
   
   initial begin
      fout = $fopen("test.bin", "w+");
      idx = 0;
      data8 = 0;
      data128 = 0;
      while (idx < 16) begin
	 $display("Data8 = %h", data8);
	 $fwrite(fout, "%z", data8);
	 data8 = data8 + 1'b1;
	 idx = idx + 1;
      end
      $fclose(fout);

      fin = $fopen("test.bin", "r+");
      while (!$feof(fin)) begin
	 code = $fscanf(fin, "%z", data128);
	 $display("Data128 = %h", data128);
      end
      $fclose(fin);

   end // initial begin
endmodule // read_mem

Output Result:

# Data8 = 00
# Data8 = 01
# Data8 = 02
# Data8 = 03
# Data8 = 04
# Data8 = 05
# Data8 = 06
# Data8 = 07
# Data8 = 08
# Data8 = 09
# Data8 = 0a
# Data8 = 0b
# Data8 = 0c
# Data8 = 0d
# Data8 = 0e
# Data8 = 0f
# Data128 = 00000000000000010000000200000003
# Data128 = 00000004000000050000000600000007
# Data128 = 00000008000000090000000a0000000b
# Data128 = 0000000c0000000d0000000e0000000f
# Data128 = 0000000c0000000d0000000e0000000f

I found two problems in the result:
1. Data written into file is not 16 (8 bits) data. It looks like each 8 bits data are extended to 32 bits.
2. When use while(!$feof(fd)) as loop, it print the last data twice.

Can anyone help me point what I did wrong in my simple code or any solutions to solve these two problems?

Thanks.

 

[sakthikumaran87]

Simple replace all %z by %h. It works fine.