jeetesh
Newbie level 4
I am getting an error as while designing an OAI22 in verilog(Xilinkx ISE 14.1) : ERROR:HDLCompilers:26 - "OAI21.v" line 26 expecting 'endmodule', found 'if'
21: module OAI21(a, b, cntrl, z);
22: input a, b, cntrl;
23: output z;
24: reg z;
25: always @(a or b or cntrl);
26: if (cntrl)
27: z = a & b;
28: else
29: z = a | b;
30: endmodule
Help me
Thanks in advance!!
21: module OAI21(a, b, cntrl, z);
22: input a, b, cntrl;
23: output z;
24: reg z;
25: always @(a or b or cntrl);
26: if (cntrl)
27: z = a & b;
28: else
29: z = a | b;
30: endmodule
Help me
Thanks in advance!!