Try with this code and let me know.
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module counter(input [31:0] baud_rate_reg,input [31:0] sys_freq,input clk,input reset,output [31:0] count_out);
wire [31:0] count_value;
assign count_value =(sys_freq/baud_rate_reg);
reg [31:0] count_out_int;
always@(posedge clk or negedge reset)
begin
if(reset==1)
count_out_int=32'b0;
else
while(count_out_int<count_value)
count_out_int=count_out_int+32'b1;
end