whats the correct encryption method in Vcs so that i can do simulation in vcs correctly by hiding hierarchy there and also those encrpted files should be understandable by DC as well.
i tried doing like this,
1. first I written pragma lines on all files ; first line is 'protect128 and last line is `endprotect128 in all verilog files
2. i encrypted all sources with the command
Code:
vcs -putprotect128 ./out -protect128 *.v
3. I done simulation without any problems , results are verified with hidden hierarchy.
4. but the DC shows an error . saying
Code:
Loading verilog file '/home/source/design_xxx.vp'
Running PRESTO HDLC
Compiling source file '/home/source/design_xxx.vp
Error: '/home/source/design_xxx.vp:1: The macro 'protected128' has not been defined. (VER-913)
*** Presto compilation terminated with 1 errors. ***
Error: Can't read 'verilog' file ''/home/source/design_xxx.vp'. (UID-59)
No designs were read
The above error lines repeated for all the files called.
how can i tell the dc to ignore the macro i.e first line or anyother way of doing encryption so that it should work on simulator and dc.
Re: verilog encryption method in VCS to hide hierarchy in simulation and to synthesiz
The latest standard for encryption is IEEE 1735 V2. Public key for a tool is required for encryption. You may need to contact tool vendor to get the key and find out whether they are supporting the standard. The files can be encrypted using any tool that supports this standard.