Non AMP

Verilog doubt regarding Z^-1 implementation

Thread starter anishsingh
Start date Apr 4, 2012

Status: Not open for further replies.

Apr 4, 2012

#1

A

anishsingh

Junior Member level 2

How do we implement a delay block in dsp systems (represented by z^-1 ) while verilog coding for semi custom asic design ??

Apr 4, 2012

#2

FvM

Super Moderator

Staff member

It's just a block of registers, possibly with a clock enable if th esampling rate is only a fraction of the system clock

Code:

always @(posedge clock)
begin
  if (sample_clk)
    x2 <= X1;
end

Status: Not open for further replies.

Similar threads

M
FPGA implementation with xilinx zynq 7000 FPGA board
- Started by mhezekiel
- Saturday at 6:26 AM
- Replies: 1
PLD, SPLD, GAL, CPLD, FPGA Design
S
PLL implementation through FPGA
- Started by sushl
- Dec 6, 2023
- Replies: 6
PLD, SPLD, GAL, CPLD, FPGA Design
C
need help with verilog coding a morse code to ascii decoder
- Started by combat5
- May 28, 2024
- Replies: 3
PLD, SPLD, GAL, CPLD, FPGA Design
K
explanation of how to translate C code into verilog
- Started by keikaku
- Mar 5, 2024
- Replies: 10
PLD, SPLD, GAL, CPLD, FPGA Design
M
How do I assign decimal values in verilog?
- Started by mahesh_namboodiri
- Jan 31, 2024
- Replies: 2
PLD, SPLD, GAL, CPLD, FPGA Design