Verilog doubt regarding Z^-1 implementation

[anishsingh]

How do we implement a delay block in dsp systems (represented by z^-1 ) while verilog coding for semi custom asic design ??

 

[FvM]

It's just a block of registers, possibly with a clock enable if th esampling rate is only a fraction of the system clock

always @(posedge clock)
begin
  if (sample_clk)
    x2 <= X1;
end