Verilog - Digital Design Help!!!

[firozjdang]

I am working on a de-serial module, and I have to collect information into a single register containing Header + Message + CRC. I am receiving serial data which will bean header of 8 bits and depending on my header bit there is a decoder which decides the length of each message and if CRC is enabled then then it might also follow by CRC bits(no lengths specified). I have to fix these variable (Header + Message + CRC) into a single register each will be of different lengths. So I am confused that how do I make a variable length register which can hold different lengths of (Header + Message + CRC).
I do not want any padding bits as the messages of longer lengths are less and more messages are of shorter length which will just increase the memory size.
I will later on add time stamp into this to make it unique. Please Help!!!!

 

[sree205]

Either your header must've some info on how long your burst is going to be or some sorta sync sequence which, if found in the data should determine that your burst has ended followed by number of bits of CRC. This is all i could come up with. If anyone has a better solution, please suggest.

 

[firozjdang]

Well I did solved it, just using the concept of state machines, I used a write state machine(40Mhz) which depends on the existing state machine (40Mhz)which filters the Headers, Messages and CRC's, this writes data sequentially into the memory then I read the data back from the memory using read state machine(48Mhz). There are plenty of flags which make the entire design look like an asynchronous fifo.

Thanks for the reply.