Verilog Digital Alarm Clock

[mehra_pallavi]

Would appreciate any kind of help with the Verilog project I'm trying to complete.

Description: Its a digital alarm clock that displays time in the LCD display format. The final output should be programmed onto a spartan 3 FPGA board.

I/O Ports:
1.) "clk"is a 256Hz clock
2.)"reset" is an asynchronous active high
3.)Key is the 4 bit key input
4.) "alarm_button" is an active high control signal for setting alarm time
5.) "time_button" is an active control signal for setting current time
6.) "sound_alarm" is an active high output
7.) "Display Time" are the outputs which display the values in LCD format
8.) "stop_watch" mode

IMAGE FOR BLOCK DIAGRAM ATTACHED



This top module has six-sub modules
a.) Time generator
b.) Key Register
c.) Alarm Register
d.) Counter
e.) Alarm Controller
f.) Display Driver


ANY help would be greatly appreciated. Thank You

 

[ads_ee]

What kind of help?...I doubt you'll find anyone here who will code this for you, unless you pay them their consultant fee (myself included).

Be more specific in your question and ask what is it that you are having a problem with. So far the top level block doesn't say much except what you have as interfaces to the design. How about drawing up a block diagram that shows the connections for the items in a-f and the control signals between them as a starting point. This should help clarify things for you.

 

[mrflibble]

How about drawing up a block diagram that shows the connections for the items in a-f and the control signals between them as a starting point. This should help clarify things for you.

Agreed. This will help you dividing your homework into smaller well defined chunks. Also, it will provide useful bits you can put in your project documentation. The block diagram and such I mean.

 

[mehra_pallavi]

Thanks for the help. I was able to write the RTL description for all the modules. Now I'd need help writing the test benches for the same. Please let me know if anybody could help me with writing the test benches if the RTL description is given?

Thanks

 

[mrflibble]

This is a good start: https://www.asic-world.com/verilog/art_testbench_writing.html