Verilog Compilation problem in module instantiation

I have a module definition (ckuclkucsisliced) as follows. I am using this (ckuclkucsisliced) multiple times in another module (ckucsislicepgd) as follows:



module ckucsislicepgd (

input pguclks10,
output [57:1] ckucsigd

);

wire [4:1] pguclks14;
wire [ 19:1] pguclks17;

ckuclkucsisliced ickuclkucsisliced_12 (
.pguclks17(\pguclks17[8] ),
.pguclks18 ("ckucsigd[24], ckucsigd[23], ckucsigd[22] ")
);
--> when I try to map part the vector ckucsigd to pguclks18, it is giving error:
"Warning-[PCWM] Port connection width mismatch
The following 328-bit expression is connected to 3-bit port "pguclks18"
of module "ckuclkucsisliced", instance "ickuclkucsisliced_12".
Expression: "ckucsigd[24], ckucsigd[23], ckucsigd[22] ""
How do I map this signal (ckucsigd) here?






module ckuclkucsisliced (
input pguclks17,
output [3:1] pguclks18

);

egl_ckdistinv ickuclkcsifslotinvs18r (
.clkin(pguclks17),
.clkout(\pguclks18[3] )
);

egl_ckdistinv ickuclkcsifslotinvs18l (
.clkin(pguclks17),
.clkout(\pguclks18[1] )
);

egl_ckdistinv ickuclkcsimslotinvs18 (
.clkin(pguclks17),
.clkout(\pguclks18[2] )
);

You can't port map this way while instantiating..

.pguclks18 ("ckucsigd[24], ckucsigd[23], ckucsigd[22] ")

this will port map it to a string... hence the problem..

Use this way

.pguclks18 (ckucsigd[24:22])

This will solve the case..

OR you can try this