If you are writing FPGA design, don't even dream about vendor-independent HDL.
You'll be digging your own grave. Actually, there is no good reason to write such HDL.
Nobody is changing FPGA vendor in the middle of project. As for ASIC prototyping, some
parts of ASIC won't be synthesised from HDL
anyway, but taken from a library (memory etc).
Vendor-independent HDL is a mistake usually made by people who come from ASIC.
regards,
Buzkiller.