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Verilog Coding Style - how to write best RTL code?

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Member level 2
Dec 30, 2001
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For reduing the debug effort,how to write best RTL code?

Well, this is a too big topic. Debugging is inevitable. But several guideline to keep RTL code consistent with netlist is that:

1. Never leave out any signal in sensitivity list in combinational block.
2. Separate combinational block from sequential block;
3. never compare any signal with 'x' or 'z';
4. Be careful about blocking and non-blocking assignment.

During debug, set some monitor signals. It will always help.

Just my two cents.

For test benches - any style will do - as long as other team members can understand it. Try to use as many notes & symbols (for variables names) as you can.
For synthesys - try to follow Synopsys HDL (Verilog) User Guide.
nLint from Novas (or Debussy) will check your code for Style (and many other pitfalls) - way before actual Synthesis - thus you will save youself a lot of design/re-design efforts/time.

Hope this helps...

If you are writing FPGA design, don't even dream about vendor-independent HDL.
You'll be digging your own grave. Actually, there is no good reason to write such HDL.
Nobody is changing FPGA vendor in the middle of project. As for ASIC prototyping, some
parts of ASIC won't be synthesised from HDL
anyway, but taken from a library (memory etc).
Vendor-independent HDL is a mistake usually made by people who come from ASIC.


Thank all of you.
Good suggestions

Be careful with full case and parallel case

Re: Verilog Coding Style

take care with parralles statements

Re: Verilog Coding Style

please read the book "reuse methodology manual". it's very useful.

Re: Verilog Coding Style care of full case
2.Thinking of post design, dont use too many DFFs and wires between modules

Verilog Coding Style

I suppose that you should know the synthesis. When you wirte the RTL , you must understand the circuit of your codes after synthesis.

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