Verilog code wont simulate properly

[user_asic]

I'm making a behavioral model of BCD to 7-segment decoder. But its does not give the predicted results. The output of all the segments are 'z'.

module binaryTo7Seg(code, segment);

output reg [7:0] segment;
input [3:0] code;

always@(code)
case(code)
       0: segment = ~8'b11111100;  
       1: segment = ~8'b01100000; 
       2: segment = ~8'b11011010; 
       3: segment = ~8'b11110010;  
       4: segment = ~8'b01100110;  
       5: segment = ~8'b10110110; 
       6: segment = ~8'b10111110;
       7: segment = ~8'b11100000;
       8: segment = ~8'b11111110; 
       9: segment = ~8'b11100110; 
      10: segment = ~8'b11101110;  
      11: segment = ~8'b00111110;
      12: segment = ~8'b10011100;
      13: segment = ~8'b01111010;
      14: segment = ~8'b10011110;
      15: segment = ~8'b10001110;
      default: segment = 8'bx;
    endcase

endmodule

module binaryTo7Seg_test(code, segment);

output reg [3:0] code;
input  [7:0] segment;

initial 
 
      begin 
 
         $monitor($time,,,"A = %b B = %b C = %b D = %b, aSeg = %b, bSeg = %b, cSeg = %b, dSeg = %b, eSeg = %b, fSeg = %b, gSeg = %b, hSeg = %b",code[3],code[2],code[1],code[0],segment[7],segment[6],segment[5],segment[4],segment[3],segment[2],segment[1],segment[0]); 
 
         #10  code[3] = 0; code[2] = 0; code[1] = 0; code[0] = 0; 
         #10  code[3] = 0; code[2] = 0; code[1] = 0; code[0] = 1; 
         #10  code[3] = 0; code[2] = 0; code[1] = 1; code[0] = 0; 
         #10  code[3] = 0; code[2] = 0; code[1] = 1; code[0] = 1; 
         #10  code[3] = 0; code[2] = 1; code[1] = 0; code[0] = 0; 
         #10  code[3] = 0; code[2] = 1; code[1] = 0; code[0] = 1; 
         #10  code[3] = 0; code[2] = 1; code[1] = 1; code[0] = 0; 
         #10  code[3] = 0; code[2] = 1; code[1] = 1; code[0] = 1; 
         #10  code[3] = 1; code[2] = 0; code[1] = 0; code[0] = 0; 
         #10  code[3] = 1; code[2] = 0; code[1] = 0; code[0] = 1;
         #10  code[3] = 1; code[2] = 0; code[1] = 1; code[0] = 0;
         #10  code[3] = 1; code[2] = 0; code[1] = 1; code[0] = 1;
         #10  code[3] = 1; code[2] = 1; code[1] = 0; code[0] = 0;
         #10  code[3] = 1; code[2] = 1; code[1] = 0; code[0] = 1;
         #10  code[3] = 1; code[2] = 1; code[1] = 1; code[0] = 0;
         #10  code[3] = 1; code[2] = 1; code[1] = 1; code[0] = 1; 
         #10 $finish; 
      end 
initial
     begin
        $dumpfile ("binaryTo7Seg.dump");
        $dumpvars (0, binaryTo7Seg_test);
     end

endmodule

Here is the result of the simulation (VCS):

0  A = x B = x C = x D = x, aSeg = z, bSeg = z, cSeg = z, dSeg = z, eSeg = z, fSeg = z, gSeg = z, hSeg = z
                  10  A = 0 B = 0 C = 0 D = 0, aSeg = z, bSeg = z, cSeg = z, dSeg = z, eSeg = z, fSeg = z, gSeg = z, hSeg = z
                  20  A = 0 B = 0 C = 0 D = 1, aSeg = z, bSeg = z, cSeg = z, dSeg = z, eSeg = z, fSeg = z, gSeg = z, hSeg = z
                  30  A = 0 B = 0 C = 1 D = 0, aSeg = z, bSeg = z, cSeg = z, dSeg = z, eSeg = z, fSeg = z, gSeg = z, hSeg = z
                  40  A = 0 B = 0 C = 1 D = 1, aSeg = z, bSeg = z, cSeg = z, dSeg = z, eSeg = z, fSeg = z, gSeg = z, hSeg = z
                  50  A = 0 B = 1 C = 0 D = 0, aSeg = z, bSeg = z, cSeg = z, dSeg = z, eSeg = z, fSeg = z, gSeg = z, hSeg = z
                  60  A = 0 B = 1 C = 0 D = 1, aSeg = z, bSeg = z, cSeg = z, dSeg = z, eSeg = z, fSeg = z, gSeg = z, hSeg = z
                  70  A = 0 B = 1 C = 1 D = 0, aSeg = z, bSeg = z, cSeg = z, dSeg = z, eSeg = z, fSeg = z, gSeg = z, hSeg = z
                  80  A = 0 B = 1 C = 1 D = 1, aSeg = z, bSeg = z, cSeg = z, dSeg = z, eSeg = z, fSeg = z, gSeg = z, hSeg = z
                  90  A = 1 B = 0 C = 0 D = 0, aSeg = z, bSeg = z, cSeg = z, dSeg = z, eSeg = z, fSeg = z, gSeg = z, hSeg = z
                 100  A = 1 B = 0 C = 0 D = 1, aSeg = z, bSeg = z, cSeg = z, dSeg = z, eSeg = z, fSeg = z, gSeg = z, hSeg = z
                 110  A = 1 B = 0 C = 1 D = 0, aSeg = z, bSeg = z, cSeg = z, dSeg = z, eSeg = z, fSeg = z, gSeg = z, hSeg = z
                 120  A = 1 B = 0 C = 1 D = 1, aSeg = z, bSeg = z, cSeg = z, dSeg = z, eSeg = z, fSeg = z, gSeg = z, hSeg = z
                 130  A = 1 B = 1 C = 0 D = 0, aSeg = z, bSeg = z, cSeg = z, dSeg = z, eSeg = z, fSeg = z, gSeg = z, hSeg = z
                 140  A = 1 B = 1 C = 0 D = 1, aSeg = z, bSeg = z, cSeg = z, dSeg = z, eSeg = z, fSeg = z, gSeg = z, hSeg = z
                 150  A = 1 B = 1 C = 1 D = 0, aSeg = z, bSeg = z, cSeg = z, dSeg = z, eSeg = z, fSeg = z, gSeg = z, hSeg = z
                 160  A = 1 B = 1 C = 1 D = 1, aSeg = z, bSeg = z, cSeg = z, dSeg = z, eSeg = z, fSeg = z, gSeg = z, hSeg = z

Is there something wrong with my testbench?

 

[wufei]

lack of this line:

binaryTo7Seg binaryTo7Seg（,,,）

 

[user_asic]

lack of this line:

binaryTo7Seg binaryTo7Seg（,,,）

Hi,

I'm not sure I can see exactly where this fits in. I Would appreciate it if you can elaborate a little. Thanks.

 

[Syswip]

Hi user_asic,

Did you look at waves?

Bests,
Tiksan
http://syswip.com/

 

[user_asic]

Hi user_asic,

Did you look at waves?

Bests,
Tiksan
http://syswip.com/

Hi Syswip,

No, I did not use the waveform viewer as yet. I was spending quite a lot of time trying to figure out my test bench.

 

[Syswip]

You can do it quickly to be sure that RTL side is OK.
By the way I simulated your code with waves and it is OK.
I think the problem is wrong dumping.

Tiksan,
http://syswip.com/

 

[absurd_jimmy]

as mentioned above, this is missing

binaryTo7Seg binaryTo7Seg(,,,)

you have not instantiated the RTL module in your test bench