Verilog code to transfer content of one memory to another of different sizes in one clock cycle.

[tipra]

I want to transfer the contents of memory 'buff' to memory 'mem'.
Memory 'buff' is of size 9 X 1 byte.
Memory 'mem' is of size 255 X 27 bytes.

I want to transfer the contents such that the content of addresses 0,3,6 of 'buff' to go in 1st, 4th ,7th, ...,25th byte from MSB of 'mem'.
Content of addresses 1,4,7 of 'buff' to go in 2nd, 5th , 8th, .. , 26th byte from MSB of 'mem'
and
Content of address 2,5,7 of 'buff' to go in 3rd, 6th ,9th,.. ,27th byte from MSB of 'mem'.
And this data should be simultaneously transferred/written to first three addresses of memory 'mem' in only one clock pulse.

I want all these data to be written in one clock cycle, i.e. I want to run the design for 1 clk cycle only.
I tried the following code. Will this work? Assume value of 'addR' is 0.

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Code Verilog - [expand]
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module(input clk, input rst);
 
reg [7:0] buff [0:8];
reg [215:0] mem [0:254];
// Assuming I have a memory 'mem' with the dimensions as stated above
// and assuming the value of reg addR at the current posedge of clk is 
//0.
always@(posedge clk)
begin
for(n=0;n<9;n=n+1)
   begin
    mem[(addR+0)][215-(24*n):208-(24*n)] <= buff[n][7:0];
    mem[(addR+1)][215-(24*n):208-(24*n)] <= buff[n][7:0];
    mem[(addR+2)][215-(24*n):208-(24*n)] <= buff[n][7:0];
   end
end

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[FvM]

Depends on the physical nature of mem. No problem if it's a huge array of registers, but impossible with a SRAM block accessed through an address bus. As you are asking in the ASIC section, I'd expect the former.

 

[tipra]

How do I achieve the given condition, provided 'mem' needs to be inferred as a memory block and not just a array of registers

 

[KlausST]

Hi,

.. a rather general question without details...

a memory block should have an interface. You need to read about it.
Usally Address lines, Data lines and control lines. And for communication you need to drive/keep the signals within their timing specifications.

I assume nobody of us can tell you, be cause we don´t have any information about the used device and the used memory section.
In either case anyone needs to read the datasheet. The fastest way is if you do this ...

Klaus

 

[ThisIsNotSam]

How do I achieve the given condition, provided 'mem' needs to be inferred as a memory block and not just a array of registers

you have to go back to the drawing board. that is not how a memory works, it has an address and a data port. you can't write to all addresses at the same time, not with conventional compiled SRAM.