Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

verilog code to decide release time

Status
Not open for further replies.

vikas.m0502

Junior Member level 1
Junior Member level 1
Joined
May 11, 2012
Messages
15
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Visit site
Activity points
1,389
Hi,

I am trying to release a signal at specific time. For that I need to write a small code in verilog.
Condition is :

if write_select is 0 for greater than 16ns then release Q after 16ns when write_select goes high.

Please let me know if need more clarification.

Thanks in advance.
Vikas
 

Perhaps you better define what you mean by "release" as it a keyword in Verilog and may have nothing to do with what you are asking.

And is this something you are trying to design, or is this to stimulate a design under test.
 

Hi Mohammed,
Thanks for your reply, but whatever is in that link i already know.
My main problem is how to give condition with respect to signal's width.


Hi Dave,
It is the same 'release' what we use as keyword.
Yes, I need this forcing for simulation purpose.
Like I said before, I have no issue with 'force' or 'release', but how to right the condition for releasing some signal based on its width.

Thanks
Vikas
 

if write_select is 0 for greater than 16ns then release Q after 16ns when write_select goes high
Task is not clear. >16ns or when write_select goes high?
I would suggest using time variable
See example code below. Adjust time_limit parameter to the timescale.

Code:
`timescale 1ns/1ns

module test1();
parameter hi = 1'b1, lo = 1'b0;
parameter time_limit = 16;
reg write_sel;
time t1, t2, time_diff;

initial
begin
	write_sel = hi;
	t1 = 0; t2 = 0; time_diff = 0;
	#10 write_sel = lo;
	#10 write_sel = hi;
	#10 write_sel = lo;
	#20 write_sel = hi;
	#10 write_sel = hi;
	#10 write_sel = hi;
	$stop;
end

always @(write_sel)
	begin
		if(write_sel)
			t2 = $time;
		else if (!write_sel)
			t1 = $time;
		if(t2>t1)
		begin
			time_diff = t2 - t1;
			if(time_diff > time_limit)
				$display("Time to release Q, duration = %d", time_diff);
		end
	end

endmodule
 

Hi vardan,

Thanks for your reply.
But your code is too lengthy. I want something precise.

What I want to do is :
If write_sel is >16ns
then whenever it goes high, 16ns after that release the force.
Means as soon as write_sel goes high, 16ns after that i have to release.
For this I need the condition which relates the width of write_sel, because write_sel toggles many times but only this time it is low for more than 16ns.

Thanks,
Vikas
 

Code:
always @(negedge write_sel)
		t2 = $time;

always @(posedge write_sel)
	if (($time-t2) > time_limit)
    $display("\n\tTime to release Q");

It's not a case to use $width. See if you can optimize the code.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top