The intra-assignment delay should also work with delay > schedule period. The RHS is evaluated immediately, the LHS assigned after the delay, creating a transport delay.
But there's no valid clock event in the above example.
As far as I understand - in VHDL one a process is entered (per sensitivity list) and a signal assignment is scheduled - any old scheduled assignments are overridden. This is UNLESS the "transport" keyword is used.
Are you saying that in Verilog all delays are transported by default?
The behavior isn't explicitly stated in the Verilog LRM, but I believe the intra-assignment delay syntax is the Verilog equivalent to VHDL transport delay.