Verilog code of 8 bit register with load facility

Status
Not open for further replies.
Re: verilog program code

do you mean something like this:

reg [7:0] my_reg;
wire [7:0] new_data;
wire load_my_reg;
always @( posedge clk )
if(load_my_reg)
my_reg <= new_data;

(you'll need to assign something to the new_data bus and the load_my_reg signal, and to take care of the clk)
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…