verilog code- modelsim hangs

Hi,
I was simulating a 4 bit structural counter in verilog.
The code is as follws, upon clicking on run modelsim is getting hung...
any ideas on wht could be happening ... ?

// 2 bit behvrl counter
module two_bit_cntr
(clk,
reset,
count
); //end of port list

//input ports
input clk;
input reset;
//output ports
output[1:0] count;
//all the input ports should be wires
wire clk;
wire reset;
// output port can be storage element or wire
reg[1:0] count;

always @ (posedge clk)
begin
if (reset == 1'b1)
count <= 2'b00;
else if (count == 2'b11)
count <= 2'b00;
else
count <= count + 1;
end
endmodule //no space between end and module

//code for dff
module dff(
d,
clk,
q,
qn
);

input d;
input clk;
output q;
output qn;

wire d;
wire clk;
reg q;
reg qn;

always @ (posedge clk)
begin
q <= d;
qn <= ~ q;
end
endmodule

//and gate definition
module and2g(
A,
B,
Z);

input A;
input B;
output Z;

wire A;
wire B;
reg Z;

always
Z <= A & B;
endmodule

//beginning of structural code
module struct_cntr(
clk,
reset,
cntr,
);

input reset;
input clk;
inout[3:0] cntr;

wire clk;
wire reset;
reg[3:0] cntr;

//internal variables
wire X;
wire Y;
wire temp;


dff u1(.clk(clk), .d(X), .q(Y), .qn(temp));
two_bit_cntr u2(.clk(clk), .reset(reset), .count(cntr[1:0]));
and2g u3(.A(cntr[1]), .B(cntr[0]), .Z(X));
two_bit_cntr u4(.clk(Y), .reset(reset),.count(cntr[3:2]));
endmodule

thnks