Verilog code implementing ALU using if statment

Hello all,
I am in urgent need to VERILOG code that implement ALU [3 input + 4output]
the ALU produces different outputs
for ex, for input 011 the output is B-C
for input 110 the output is A nor B nor c

Hi here is a Basic skeleton of the program you can improve ....

module simplealu(a,b,c,opcode,result);
input [3:0] a;
input [3:0] b;
input [3:0] c;
input [2:0] opcode;
output [3:0] result;
reg [3:0] result;

//behaviour of ALU
//combinational ALU

always@(a or b or c or opcode)
begin
if(opcode==3'b000)
result=a+b+c; //addition
if(opcode==3'b001)
result=a&b&c; //AND
if(opcode==3'b010)
result=a|b|c; //OR
if(opcode==3'b011)
result=a^b^c;// XOR
if(opcode==3'b100)
result=~a; //COMPLEMENT
if(opcode==3'b101)
result=a*b*c;//MULTIPLY
if(opcode==3'b110)
result=a-b-c;//SUBTRACT

else
result=4'b0000; //DEFAULT
end
endmodule

Hi,
U might also want to refer this text book called "Digital Design and Computer Architecture" by authors David Harris and Sarah Harris.
Excellent book for Verilog ( chapter 4 )

Refer Verilog book by Samir Palnitkar....Highly recommended for HDL coding