how to write verilog code for scan d flipflop using 2*1multiplexers as the scan logic .......for dft process...
kindly helpme out in writing the code ...
how to write verilog code for scan d flipflop using 2*1multiplexers as the scan logic .......for dft process...
kindly helpme out in writing the code ...
Question is misguided. There is no need to code flip-flops in RTL. You want the tools to infer them from your code, never to describe the flop functionality yourself. Also doesn't matter if this is for FFT or any other logic, question remains pointless.
Also remember that the components that make up the FPGA fabric have been chosen for you. You can't map to something that isn't there already.
I am guessing that you would want this inside the ASIC forum.
Your flops are already inferred from your RTL code.
In ASIC development, The DFT tool replaces the normal flops by scan-flops. Nothing needs to be written in Verilog/VHDL.