[SOLVED] Verilog code for N-bit Gray to Binary conversion

[sharanyakhamithkar]

Hi guys,
I was trying to write a RTL code for Gray to Binary conversion for N number of bits.

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Code Verilog - [expand]
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module gray2binary(gr,bi);
 
parameter N=4;
input [N-1:0]gr;
output reg [N-1:0]bi;
integer i=N-2;
  
always @(*)
  begin
    bi[N-1]=gr[N-1];
    for (i=N-2;i==0;i=i-1)
      $display("Entering for loop");
      bi[i]=gr[i]^bi[i+1];
  end
      
endmodule

---

For this code, i am getting output of first two MSB bits, other two bits are coming as dont cares(X's).
Please let me know what went wrong?

 

[dpaul]

1. Learn to use google search. I won't give you the link but my search phrase "n bit gray to binary conversion + verilog" comes up with what you need.
2. You are using Verilog like a s/w language (use of for loop). Learn Verilog properly.

 

[sharanyakhamithkar]

1. Learn to use google search. I won't give you the link but my search phrase "n bit gray to binary conversion + verilog" comes up with what you need.
2. You are using Verilog like a s/w language (use of for loop). Learn Verilog properly.

I understand. Thanks and Ofcourse i have asked here after trying on google. If it is not for n-bits, i am getting output and finding online for the same. If it is generic conversion, which is N-bit, i am not finding anywhere, which is why i have asked in this forum!

- - - Updated - - -

Hi guys,

I have solved this. I have used generate and endgenerate. Anyways thanks dpaul.

 

[FvM]

For-loop as in post #1 can be used to generate combinational logic. Problem is simply wrong exit condition. You probably meaned to write i>=0.

 

[ads-ee]

Just to help someone else who might be searching for the same thing...

Here is a modified and fixed version of the code using the preferred Verilog 2001 syntax for module ports

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module gr2bi #(
  parameter   N = 4
) (
  input       [N-1:0]   gr,
  output reg  [N-1:0]   bi
);
 
  integer i = N-2;
  
  always @(*) begin
    bi[N-1] = gr[N-1];
    for (i=N-2;i>=0;i=i-1)
      bi[i] = gr[i] ^ bi[i+1];
  end
      
endmodule

---

and here is a testbench that proves it works.

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`timescale 1ns/1ps
module tb;
 
  parameter N = 4;
 
  reg   [N-1:0]   gr;
  wire  [N-1:0]   bi;
 
  initial begin
    gr = 0;
    repeat (2**N) begin
      #10;
      gr = gr + 1;
    end
  end
 
  gr2bi  #(
    .N    (N)
  ) UUT (
    .gr   (gr),
    .bi   (bi)
  );
 
endmodule

---

- - - Updated - - -

Actually here is my preferred version of both an N-bit binary-to-gray and N-bit gray-to-binary conversion.

binary to gray

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module b2g #(
  parameter   N = 4
) (
  output  [N-1:0]   g,
  input   [N-1:0]   b
);
 
  assign g = b ^ (b >> 1);
 
endmodule

---

gray to binary:

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module g2b #(
  parameter   N = 4
) (
  output  [N-1:0]   b,
  input   [N-1:0]   g
);
  generate genvar i;
    for (i=0; i<N; i=i+1) begin : gen_bin
      assign b[i] = ^g[N-1:i];
    end
  endgenerate
 
endmodule

---

Testbench:

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`timescale 1ns/1ps
module tb;
 
  parameter N = 4;
 
  reg   [N-1:0]   bin;
  wire  [N-1:0]   gray;
  wire  [N-1:0]   binary;
 
 
  initial begin
    bin = 0;
    repeat (2**N) begin
      #10;
      bin = bin + 1;
    end
  end
 
 
  // my preferred versions of both conversions
 
  // binary to gray
  b2g #(.N(N)) uut_b2g (
    .g  (gray),
    .b  (bin)
  );
 
  // gray to binary
  g2b #(.N(N)) uut_g2b (
    .b  (binary),
    .g  (gray)
  );
 
  initial begin
    $monitor ("binary = %b, gray = %b, binary %b", bin, gray, binary);
  end
 
endmodule

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Note: this gray to binary conversion doesn't require the feedback of the bi[i+1] to produce the bi bit (it only relies on the gray value). Haven't tried synthesizing both my preferred version and the modified original, but it seems to me the one with the feedback might result in something slightly slower as the bi bits have to propagate through the bit width of the converted value. Then again synthesis may end up with the same circuit in the end.