verilog code for following circiut?? help me!!!!!!!

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harinisas

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hi i am writing a code for a circuit where the input to the 16 bit carry look ahead adder is output of the d flipflop and input to the flipflop is output of the adder its like a loop when i am writing the code i am unable to see the output so please help me its urgent i want the code in verilog.
 

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Hiiii harinisas,
If u cant see the output in waveform then there might be a combinational loop.... so checkout for these...
> I will give an example if declare a,b as wire's let 'c' be some other variable...
>> assign a = c & b ;
>> assign b = c | a ;
>> assign a = a & b;
If u see in the above assignments there is a loop as they goes on changes irrespective of clock and this creates a loop.... so check for these kind of loops...
 

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code for the circuit help me!!!!!!!1

hi i am writing a code for a circuit where the input to the 16 bit carry look ahead adder is output of the d flipflop and input to the flipflop is output of the adder its like a loop when i am writing the code i am unable to see the output so please help me its urgent i want the code in verilog. and the inverter should give me output when i enable a signal and also reset the adder. help me its urgent.
 

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  • cirut.jpeg
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