And of course you should know that, free has always some limitations. I mean you have to review some parts of the code and make sure that every thing is OK.
In www.opencores.org, you'll find a free 10/100 ethernet controller verilog source codes package. But it is rather a functional model than synthesizable models because of a lot of time latecy statements in the codes, such as #1ns...
In www.opencores.org, you'll find a free 10/100 ethernet controller verilog source codes package. But it is rather a functional model than synthesizable models because of a lot of time latecy statements in the codes, such as #1ns...