I am a newbie in Verilog and I wanted to make a code to display the functions of the 74LS190 which is an Up/Down Counter. 74LS190 is a synchronous Up/Down BCD Counter in which the state changes of the counter are synchronous with the LOW-to-HIGH transition of the Clock Pulse Input. I wanted to code something like it will count up from 0 to 9 then back to 0 and count down from 9 to 0 then back to 9. Any help? Can you check the code below if it answers my question and if not, any way I can modify the code?
module up_down_counter (
out ,// Output of the counter
up_down ,// up_down control for counter
clk ,// clock input
data ,// Data to load
reset // reset input);//----------Output Ports--------------output[9:0] out;//------------Input Ports-------------- input[9:0] data;input up_down, clk, reset;//------------Internal Variables--------reg[9:0] out;//-------------Code Starts Here-------always@(posedge clk)if(reset)begin// active high reset
out <=10'b0;endelseif(up_down)begin
out <= out +1;endelsebegin
out <= out -1;endendmodule
Quartus II has a visual interface to make easy you draw the stimuli signals, but it is actually saved within a file in the same language set as the default in project. Regardless, the simulation is that will allow you determine whether it's working properly or not.
Quartus II has a visual interface to make easy you draw the stimuli signals, but it is actually saved within a file in the same language set as the default in project. Regardless, the simulation is that will allow you determine whether it's working properly or not.
I didn't see where in the code you ensure that conting will not exeed 9.
Hi, can you check the code below? I wanted to make an up/down counter that will count up from 0 to 9 then back to 0 and/or count down from 9 to 0 then back to 9.
It sounds as if you had disregarded the previous recommendation to yourself make the simulation to check the working of code. Did you at least compiled this code ? Taking a quick look did not seem to be anything out of place I but could be wrong; anyway the code lenght certainly could be reduced by using simpler implementations ( e.g reloading data_out variable at overflow/underflow, I guess ). In addition, once it has in lines 38 and 53 a time dependent statement #, it is assumed it will work only in simulation environment, right ?
I did simulate the code and it run with no errors. The code above was for 74LS191 and I wanted to modify it because I wanted to implemet 74LS190. When I simulated the code, it counted from 0 to 15. What I wanted to make is after 9, it will go back to 0. What do you think shall I do with code to do this?