[SOLVED] Verilog code error - Illegal reference to net

[vreg]

module system(r,g,y,counter);
  output reg r,g,y;
  input [3:0] counter;

  always @ (counter)
  if (counter >= 4'b1011 && counter <= 4'b1111)
    begin
      counter = 4'b0000;
      g = 0;
      y = 0;
      r = 0;
    end
  else if (counter >= 4'b1001 && counter < 4'b1011)
    begin
      g = 0;
      y = 0;
      r = 1;
    end
  else if (counter >= 4'b1000 && counter < 4'b1001)
    begin
      g = 0;
      y = 1;
      r = 0;
    end
  else
    begin
      g = 1;
      y = 0;
      r = 0;
    end

endmodule

Illegal reference to net "counter" on line no. 8
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counter is an input