verilog define parameter
`define is a macro. You use it in the same way that you use macros in C language.
A parameter, on the other hand, will become a membor of your module. Imagin you write a code for a generic adder with a WIDTH parameter as the width of its input/output ports. Now, you can instantiate the same adder several times with a different value for the WIDTH parameter.
Example
module adder (a,b,c);
parameter WIDTH = 2; //defult value
input [WIDTH-1:0] a;
input [WIDTH-1:0] b;
output [WIDTH-1:0] c;
assign c=a+b;
endmodule
The instantiation will look like this:
adder #( 4 ) adder1 (a,b,c); // a four bit adder
adder #( 8 ) adder1 (a,b,c); // an eight bit adder
Now, think about it, could you do the above example, using macros?