sotomie
Newbie level 6
can anyone please tell me if there is any logical error is this always block,its for fibonacci series ,i'm getting my results right but i was just curious if i've done something which isn't correct like using two 'if's?
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 always@(posedge clock) begin if(n==0) current=1; else begin temp=current; current=current+previous; previous=temp; end if(current<previous) begin previous=0; n=0; current=1; end n=n+1; end endmodule
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