can anyone please tell me if there is any logical error is this always block,its for fibonacci series ,i'm getting my results right but i was just curious if i've done something which isn't correct like using two 'if's?
always@(posedge clock)
begin
if(n==0)
current<=1;
else
begin
temp=current;
current=current+previous;
previous=temp;
end
if(current<previous)
begin
previous<=0;
n<=0;
current<=1;
end
n<=n+1;
end
endmodule
can you modify it ? I'm new to verilog.And if i am changing all the blocking assignments to non-blocking results are not right because of this part i think