vijay82
Member level 2
verilog case statement
Is is proper coding convention to use a case statement inside an always @posedge clk block? . Something like
always @(posedge clk or negedge rst_n)
if (rst_n == 1'b0)
<reset logic>
else
case < case variable >
<some logic>
.
.
.
endcase
It works all right, but I haven't seen any professional examples so far.
Thanks for any answers.
Is is proper coding convention to use a case statement inside an always @posedge clk block? . Something like
always @(posedge clk or negedge rst_n)
if (rst_n == 1'b0)
<reset logic>
else
case < case variable >
<some logic>
.
.
.
endcase
It works all right, but I haven't seen any professional examples so far.
Thanks for any answers.