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Verilog : bit mask to index converter

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madushan

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Hi guys,
Can anyone please help me to design the following circuit

let's say that there's an array of 4 bits (the width of this array should be parameterizable)
I need to find the index of the first occurrence of a '1' in this array when searched from the least significant bit
So
if array is 0100 module should return index 2
if array is 1100 module should return index 2
if array is 1110 module should return index 1
if array is 1111 module should return index 0

I need to do this in combinational manner
please help
Thanks
 

madushan

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I can simply use a series of if else if statements, like
Code:
if (array[0]) begin
   index <= 0;
end
else if (array[1]) begin
   index <= 1;
end
else if (array[2]) begin
   index <= 2;
end
.....
.....
Thss doesn't suit here because the width of this array must be parameterizable, it can be 5, 6, 32, 64, etc
 

Madushan.UoM

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What should the result be if there are no bits set?
oh sorry,
if the all the bits are 0s, index should be 0

so this changes to
if array is 0100 module should return index 3
if array is 1100 module should return index 3
if array is 1110 module should return index 2
if array is 1111 module should return index 1
 

permute

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hmm, my first thought is to (-x) & (x), which returns the rightmost set bit as a vector:

0011101000 = x
1100010111 = ~x
1100011000 = -x
0000001000 = -x&x

This might be helpful if x is locally generated (the -x infers an adder which is a local structure and may cause routing bottlenecks in some cases). If you don't need an encoded version, this may work well.
 

dave_59

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This is synthesizable because there is an upper bound on the number of loops, but I don't know if all synthesis tools support this:

SystemVerilog
Code:
parameter SIZE = 10;
bit array[SIZE];
int i;
always_comb 
    begin
       i=0;
       while (i<SIZE && !array[i]) i++;
    end
Verilog
Code:
parameter SIZE = 10;
reg array[0:SIZE-1];
integer i;
always @(array); 
    begin
       i=0;
       while (i<SIZE && !array[i]) i=i+1;
    end
 
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