Thanks for your response.
Do you mean that during the simulation, 'always @' will compile first and the if loop will compile after that?
So while the simulator reaches the line 'if (reset == 1'b1)', the 'posedge reset' has been checked and reset has rised up to 1 already.
Therefore, if I want to reset the circuit and change reset value from 0 to 1, when the compiler reach 'if (reset == 1'b1)', the reset value here is the one after the rising edge, which is 1.
When you say there is no edge detection involved, do you mean there is no Verilog code for edge detection component? I am wondering why 'always @ posedge' is not edge dection?