Verilog assignment query

[vcnvcc]

Input [3:0]Flow;

assign {a_flow, b_flw, c_flow} = { flow[‘a_flow], flow[`b_flow], flow[‘c_flow] };

I donot understand it – can you please help

Does it mean


assign {a_flow, b_flw, c_flow} = flow[3], flow[2], flow[1]
OR
assign {a_flow, b_flw, c_flow} = flow[2], flow[1], flow[0]


Thanks

 

[FvM]

You forgot to show the definition of macros a_flow, b_flow, c_flow. Looking at it, you can probably answer the question yourself.