Aug 1, 2017 #1 H hareeshP Member level 3 Joined Jul 19, 2017 Messages 59 Helped 1 Reputation 2 Reaction score 1 Trophy points 8 Activity points 491 Hi All, Please anyone tell me how the below code works? Code Verilog - [expand]1 assign Reset = (a & cnt[19])? (ok_cnt[19]? b: 1'b1) : b;
Hi All, Please anyone tell me how the below code works? Code Verilog - [expand]1 assign Reset = (a & cnt[19])? (ok_cnt[19]? b: 1'b1) : b;
Aug 1, 2017 #2 T TrickyDicky Advanced Member level 7 Joined Jun 7, 2010 Messages 7,110 Helped 2,081 Reputation 4,181 Reaction score 2,048 Trophy points 1,393 Activity points 39,769 Reset is assigned based on the conditions on the RHS. ? is the conditional operator in verilog: (condition) ? (value when condition_is_true) : (value when condition_is_false); Remember in verilog, like C, any non-zero value counts as true. - - - Updated - - - Btw - google will get you many Verilog tutorials - here is the first hit for me: https://www.asic-world.com/verilog/veritut.html
Reset is assigned based on the conditions on the RHS. ? is the conditional operator in verilog: (condition) ? (value when condition_is_true) : (value when condition_is_false); Remember in verilog, like C, any non-zero value counts as true. - - - Updated - - - Btw - google will get you many Verilog tutorials - here is the first hit for me: https://www.asic-world.com/verilog/veritut.html
Aug 1, 2017 #3 H hareeshP Member level 3 Joined Jul 19, 2017 Messages 59 Helped 1 Reputation 2 Reaction score 1 Trophy points 8 Activity points 491 can you please convert the above code into vhdl?
Aug 1, 2017 #4 T TrickyDicky Advanced Member level 7 Joined Jun 7, 2010 Messages 7,110 Helped 2,081 Reputation 4,181 Reaction score 2,048 Trophy points 1,393 Activity points 39,769 hareeshP said: can you please convert the above code into vhdl? Click to expand... Following through the Verilog tutorials should mean you could do this yourself.
hareeshP said: can you please convert the above code into vhdl? Click to expand... Following through the Verilog tutorials should mean you could do this yourself.
Aug 2, 2017 #5 H hareeshP Member level 3 Joined Jul 19, 2017 Messages 59 Helped 1 Reputation 2 Reaction score 1 Trophy points 8 Activity points 491 actually i am following the vhdl tutorial and i wants convert a verilog source code into vhdl one. So i need to understand the logic used in verilog.
actually i am following the vhdl tutorial and i wants convert a verilog source code into vhdl one. So i need to understand the logic used in verilog.